The present invention relates to methods for producing semiconductor devices, semiconductor lasers, and quantum wire structures, an apparatus for producing semiconductor devices, and crystal growth methods, and more particularly to methods including a dry etching process and an epitaxial growth process.
Recently, in manufacturing semiconductor laser diodes or quantum wire structures, a fine structure producing technique utilizing etching and regrowth has been developed. More specifically, this technique includes selectively etching away a portion of a crystal layer and growing an epitaxial layer on the surface of the crystal layer exposed by the etching, which epitaxial layer is electrically and optically different from the crystal layer, whereby a desired electronic state is achieved. In this process, forming a fine structure in desired shape with high controllability and maintaining a clean regrowth interface are very important. Especially when AlGaAs is employed as a material of the device, since Al is an easily oxidizable material, an oxide film formed on the surface adversely affects the etching process, resulting in a fine structure of unwanted shape. In addition, since the regrowth interface is contaminated, the quality of a regrown crystal layer is significantly deteriorated. These problems must be solved when the technique is employed in the manufacture of the devices.
Japanese Published Patent Application No. 58-53834 discloses a prior art method for etching an AlGaAs layer by reactive dry etching. In this method, a GaAs cap layer disposed on the AlGaAs layer prevents the surface of the AlGaAs layer from being oxidized. This prior art describes that a favorable AlGaAs etching is achieved for the first time when the reactive dry etching is performed from the GaAs cap layer. Japanese Published Patent Application No. 61-184892 also discloses an AlGaAs etching method employing a GaAs cap layer. In this prior art, the AlGaAs layer with the GaAs cap layer is etched by HCl gas.
A description is given of problems in the prior art AlGaAs etching method employing the GaAs cap layer.
FIGS. 30(a)-30(c) and 31(a)-31(c) are sectional views for explaining experiments conducted to confirm the effects of the prior art AlGaAs etching method. In the figures, reference numeral 1 designates a regrown GaAs layer, numeral 2 designates an AlxGa1xe2x88x92xAs layer, numeral 23 designates a GaAs substrate, and numeral 211 designates a GaAs cap layer. A first sample and a second sample are formed according to the process steps illustrated in FIGS. 30(a)-30(c) and FIGS. 31(a)-31(c), respectively.
Initially, as illustrated in FIG. 30(a), the AlxGa1xe2x88x92xAs layer 2 and the GaAs cap layer 211 are successively grown on the GaAs substrate 23 by MOCVD (first crystal growth of the first sample). On the other hand, in the step of FIG. 31(a), only the AlxGa1xe2x88x92xAs layer 2 is grown on the GaAs substrate 23 by MOCVD (first crystal growth of the second sample). The AlxGa1xe2x88x92xAs layer 2 is 2 xcexcm thick and the GaAs cap layer 211 is 0.1 xcexcm thick. The first and second samples are taken out from the reaction chamber and left in the air for a few days. Thereafter, each of the first and second samples is etched by 1 xcexcm from the surface using HCl gas (FIGS. 30(b) and 31(b)) and, subsequently, in the same reaction chamber, the GaAs layer 1 is grown to 2 xcexcm by MOCVD (FIGS. 30(c) and 31(c)).
FIGS. 32(a) and 32(b) illustrate SIMS (Secondary Ion Mass Spectroscope) profiles of impurity ion concentrations in the vicinity of the regrowth interface, i.e., the interface between the AlxGa1xe2x88x92xAs layer 2 and the regrown GaAs layer 1. FIG. 32(a) illustrates the SIMS profile of the first sample shown in FIG. 30(c) and FIG. 32(b) illustrates the SIMS profile of the second sample shown in FIG. 31(c). In the figures, reference numeral 1 designates the regrown GaAs layer, numeral 2 designates the AlxGa1xe2x88x92xAs layer, and numeral 3 designates the regrowth interface. In both samples, segregations of oxygen (O) and chlorine (Cl) are observed in the vicinity of the regrowth interface. In addition, the dislocation density of the regrown GaAs layer 1 of the first sample is 5xc3x97105/cm2 and that of the second sample is 5xc3x97108/cm2.
These results are construed as follows. In the second sample, since the etching is started from the AlxGa1xe2x88x92xAs layer 2 whose surface is oxidized, the oxide film on the surface reacts with Cl during the etching, and the products are attached to the wafer surface and segregated on the regrowth interface 3. The segregations of O and Cl on the regrowth interface 3 adversely affect the quality of the regrown GaAs layer 1.
On the other hand, in the first sample with the GaAs cap layer 211, since the cap layer prevents the surface of the AlxGa1xe2x88x92xAs layer 2 from being oxidized, segregations of O and Cl in the vicinity of the regrowth interface 3 are reduced compared to the second sample, which means that the GaAs cap layer 211 improves the quality of the regrown GaAs layer 1.
However, the segregations of O and Cl on the regrowth interface are not completely prevented by the GaAs cap layer as shown in FIG. 32(a), and the dislocation density of the regrown GaAs layer of the first sample, i.e., 5xc3x97105/cm2, is, by one order of magnitude, higher than 1xc3x97104 pieces/cm2 that is a typical dislocation density required for a compound semiconductor device. This result shows that even a slight oxide film formed on the surface of the GaAs cap layer causes the segregations of O and Cl on the regrowth interface.
That is, the GaAs cap layer alone cannot provide a clean regrowth interface of the AlGaAs layer. Therefore, it is difficult to attain a clean regrowth interface and a high-quality regrown GaAs layer by the prior art etching method disclosed in Japanese Published Patent Application No. 58-53834.
FIG. 34 is a schematic diagram for explaining a vapor phase etching method disclosed in Japanese Published Patent Application No. 62-153199. In the figure, reference numeral 241 designates a reactor, numeral 242 designates a pedestal, numeral 243 designates a semiconductor substrate, numeral 244 designates a resistance heating means, numeral 245 designates a bypass pipe, numeral 246 designates a low temperature region, numeral 247 designates a high temperature region, and numeral 248 designates an etching gas inlet.
In this etching method, initially, HCl gas is sufficiently applied to the surface of the semiconductor substrate 243 in the low temperature region 246. Then, the substrate 243 is moved to the high temperature region and, after a prescribed time, it is returned to the low temperature region 246. This is one cycle of the etching process. In the low temperature region 246 at about 400xc2x0 C., the substrate 243 is not etched by the HCl gas but Cl is adsorbed by the substrate. When the substrate is moved to the high temperature region 247 at about 600xc2x0 C., the adsorbed Cl escapes from the surface as GaCl3, whereby a monomolecular layer level etching is carried out with high controllability.
However, this prior art vapor phase etching method has the following drawbacks.
In this etching method, the wafer is moved between the low temperature region and the high temperature region and, in each region, it is left for a prescribed time until the substrate temperature reaches a desired temperature. Therefore, one cycle of the etching takes a few minutes, providing a very low etching rate. In addition, since it is difficult to control separations of As atoms and Ga atoms from the GaAs surface separately from each other, the etching is not smoothly carried out.
FIG. 35 is a sectional view illustrating a quantum wire laser structure disclosed in Applied Physics Letters, 55(1989), pp. 2715-2717. In the figure, reference numeral 250 designates an n+ type GaAs substrate. There are successively disposed on the GaAs substrate 250 an n type AlyGa1xe2x88x92yAs first cladding layer 251, an AlxGa1xe2x88x92xAs barrier layer 252, a GaAs quantum well layer 253, an AlxGa1xe2x88x92xAs barrier layer 254, a p type AlyGa1xe2x88x92yAs second cladding layer 255, a p+ type GaAs cap layer 256, and a Ti/Au electrode 257. An active layer 260 comprises the well layer 253 and the barrier layers 252 and 254. Reference numeral 258 designates high resistance regions formed by ion implantation. Reference numeral 259 designates an active region in which a quantum wire structure is formed.
In production, there are successively grown on the n+ type GaAs substrate 250 having a stripe-shaped V groove, the n type AlyGa1xe2x88x92yAs first cladding layer 251, the active layer 260 comprising the GaAs well layer 253 and the AlxGa1xe2x88x92xAs barrier layers 252 and 254, the p type AlyGa1xe2x88x92yAs second cladding layer 255, and the p+ type GaAs cap layer 256. Then, dopant impurity ions are selectively added to portions of the second cladding layer 255 and the cap layer 256, forming the current narrowing layers 258.
While the active layer forms a quantum well structure on the flat surface of the substrate, it forms a quantum wire structure 259 at the bottom of the V groove.
The quantum wire structure 259 will be described in more detail. In FIG. 35, the GaAs substrate 250 has a (100) surface orientation. Since the stripe-shaped V groove is formed along the [0{overscore (1)}1] direction by conventional photolithography and wet etching, a (111) A plane is exposed at opposite side walls of the V groove. Under the typical growth conditions of MOCVD (Metal Organic Chemical Vapor Deposition), the growth rate on the (100) surface is approximately equal to the growth rate on the (111) A surface. Therefore, the crystal layers 251 to 256 are grown parallel to each other along the V groove as shown in FIG. 35. Since the bottom end of the V groove is rounded, the (100) surface is partially exposed. Therefore, on the very narrow region at the bottom of the V groove where the (100) surface is exposed, the crystal growth proceeds perpendicularly to the (100) surface, so that the crystal layer grown on that region is thicker than the crystal layer grown on the side surfaces of the groove. In this way, the GaAs quantum well layer 253 forms the crescent-shaped quantum wire 259 at the bottom of the V groove.
However, this prior art laser structure has the following drawbacks. Since the crescent-shaped quantum wire 259 is formed continuously on the quantum well structure formed on the side surfaces of the V groove, the active region has the electron states of both the quantum well and the quantum wire, resulting in a multimode oscillation of the laser. Further, since the quantum wire is united with the quantum well, it is difficult to bring out characteristics of the quantum wire independently. Therefore, in this prior art, it is difficult to produce a plurality of quantum wires of uniform characteristics with high controllability and reproducibility.
FIG. 33 is a perspective view illustrating a part of a high-power semiconductor laser with window layers grown on cleaved facets, disclosed in Japanese Journal of Applied Physics, Vol. 30, 1991, pp. L904xcx9cL906. In the figure, reference numeral 231 designates a p type GaAs substrate. There are successively disposed on the substrate 231 an n type GaAs current blocking layer 232, a p type Al0.33Ga0.67As cladding layer 233, a p type Al0.08Ga0.92As active layer 244, an n type Al0.33Ga0.67As cladding layer 235, and an n type GaAs contact layer 236. Reference numeral 237 designates a cleaved (110) facet, and numeral 238 designates an undoped Al0.4Ga0.6As window layer grown on the cleaved (110) facet 237.
The window structure employed in this prior art laser will be described in more detail.
In the AlGaAs high-power laser, a lot of surface states are produced at the oscillation facets. The surface states reduce the energy band gap in the vicinity of the facets compared with the energy band gap in the center of the laser. Therefore, regions in the vicinity of the facets become light absorption regions with respect to the wavelength of the laser light, and the localized heat generation in the light absorption region is increased with an increase in the light output. Since the energy band gap is reduced with the temperature rise, the absorption of laser light is further encouraged, increasing the temperature at the facet, i.e., so-called positive feedback occurs. If the temperature rise is sufficient, localized melting of the semiconductor materials can occur, resulting in catastrophic optical damage (COD) that destroys the laser. In order to reduce the light absorption at the oscillation facets of the laser and increase the power level without risk of COD, window layers having energy band gap larger than that equivalent to the oscillation wavelength of the laser are formed on the facets.
In the prior art high-power laser, the window layers 238 are formed according to the process steps described in the following. Initially, the laser structure is fabricated using conventional wet etching and LPE growth. More specifically, after growing the n type GaAs current blocking layer 232 on the p type GaAs substrate 231, the stripe-shaped V groove is formed in the center of the wafer penetrating through the current blocking layer 232. Then, the p type Al0.33Ga0.67As cladding layer 233, the p type Al0.08Ga0.92As active layer 244, the n type Al0.33Ga0.67As cladding layer 235, and the n type GaAs contact layer 236 are successively grown on the wafer. After grinding the wafer to a desired thickness, the wafer is cleaved in a plurality of bars each having a width equal to the resonator length of the laser. The resonator length of a typical high-power laser is 300xcx9c600 xcexcm. Then a material having an energy band gap larger than the energy band gap equivalent to the oscillation wavelength is deposited on a part of the bar-shaped wafer corresponding to the resonator facet, preferably by MOCVD.
In this prior art laser, since the laser oscillation wavelength is 830 nm, which is equivalent to 1.49 eV, the undoped Al0.4Ga0.6As layer 238 having an energy band gap of about 1.93 eV is employed as the window layer. After forming electrodes and coating the window layers, the bar-shaped wafer is divided into a plurality of chips, completing the laser device shown in FIG. 33. The prior art literature, i.e., Japanese Journal of Applied Physics, Vol.30, 1991, pp. L904xcx9cL906, describes that the window layers prevent COD and increase the output power and life time of the laser.
However, the prior art laser with the window layers has the following drawbacks.
In fabricating semiconductor lasers, generally, process steps until the formation of electrodes are carried out on a wafer to secure mass production with high reproducibility. That is, the production method of this prior art, in which the window layers are formed on portions corresponding to resonator facets after cleaving the wafer in a plurality of bars each having a width equivalent to the resonator length, provides very poor productivity, so that this method is not industrially available. Further, when the window layers are formed by MOCVD after the formation of the resonator facets by cleaving, the cleaved facets are easily oxidized and surface states are produced thereon so long as the cleaving is performed in the air. Since the surface states on the facets adversely affect the effect of the window layers, the process steps from the cleaving to the growth of the window layers have to be carried out in inactive gas or in vacuum.
The reason why the prior art laser is fabricated in such complicated process will be described.
Since the resonator facets of the laser also serve as laser light reflecting facets, they must be optically flat. In addition, they must be perpendicular to the resonator length direction. Therefore, the prior art method, in which a semiconductor substrate having a (100) surface orientation is employed and the resonator facets perpendicular to the (100) surface are formed by cleaving, has been proposed and employed as a general production method. However, with the advance of developments of high power and multifunction semiconductor lasers, a technique for fabricating resonator facets of lasers without cleaving the wafer has been desired, and facet formation methods utilizing dry etching, such as reactive ion etching (RIE), have been developed. However, the present RIE technique has the problem of physical damage due to the collision of ions, that adversely affects the quality of crystal layers at the resonator facets, although perpendicular facets can be produced by RIE. Further, it is difficult to produce a facet as smooth as a cleavage plane. Therefore, the facet formation technique using RIE is not yet established. For the reasons described above, the oscillation facets are formed by cleaving at present.
FIGS. 36(a) to 36(e) are sectional views illustrating process steps in a method for fabricating a semiconductor laser disclosed in, for example, IEEE Journal of Quantum Electronics, Vol. 23, 1987, p. 720.
Initially, there are successively grown on an n type GaAs substrate 300 an n type GaAs buffer layer 301, an n type AlGaAs cladding layer 302, an undoped GaAs active layer 303, a p type AlGaAs cladding layer 304, and an n type GaAs current blocking layer 305. These layers are grown by MOCVD on a substrate with a (100) surface orientation. Thereafter, an SiO film 306 is deposited on the current blocking layer 305 by sputtering and patterned by conventional photolithography to form a stripe-shaped opening along the [0{overscore (1)}1] direction (FIG. 36(a)).
In the step of FIG. 36(b), the n type GaAs current blocking layer 305 is etched using a tartaric acid etchant, forming a stripe-shaped groove. In this etching process, a very thin portion of the current blocking layer 305 is left at the bottom of the groove. If the etching is carried out until the surface of p type.AlGaAs cladding layer 304 is exposed at the bottom of the groove, the exposed surface is unfavorably oxidized in air, adversely affecting a crystal layer grown thereon. In addition, (111)A planes are exposed on the opposite side surfaces of the groove.
In the step of FIG. 36(c), the wafer is put in a reactor of an MOCVD apparatus, and the portion of the current blocking layer 305 remaining at the bottom of the groove is selectively removed by vapor phase etching using HCl gas and AsH3 gas.
Subsequently, in the same reactor, a p type AlGaAs cladding layer 307 is selectively grown in the groove by MOCVD (FIG. 36(d)). As shown in FIG. 36(d), the p type AlGaAs cladding layer 307 is not grown with a flat surface. The reason will be described using FIG. 37. As shown in FIG. 37, the growth of the cladding layer 307 starts from the opposite side surfaces of the groove, i.e., the (111)A planes, and from the flat bottom surface of the groove, i.e., the (100) surface. After the groove is completely filled with the layer 307, the growth proceeds forming the (111)B plane that forms an angle of about 54xc2x0 with respect to the (100) surface, resulting in the uneven surface of the cladding layer 307.
After removing the SiO film 306 using a hydrogen fluoride (HF) etchant, a p type GaAs contact layer 308 is grown by MOCVD (FIG. 36(e)). Even if the p type GaAs contact layer 308 is grown thick as shown in FIG. 36(e), the wafer surface remains uneven.
In this prior art method, the uneven surface of the wafer adversely affects the processing after the crystal growth, for example, photolithography for patterning an upper electrode. Further, if the semiconductor laser fabricated by this prior art method is adhered to a heat sink with the p type GaAs contact layer in contact with the heat sink (junction down), compressive stress is applied to the active layer, reducing the reliability of the laser.
By the way, a technique for growing a crystal layer on a different kind substrate is a key technology for realizing an advanced information processing device, for example, a hybrid IC including an Si electron device and a compound semiconductor light emitting device. Therefore, this crystal growth technique has been extensively studied in many laboratories. Especially a technique for growing GaAs layer on Si has been desired because it has very wide application. In the growth of GaAs on Si, however, unwanted stress is applied to the GaAs layer due to a difference in thermal expansion coefficients between GaAs and Si, resulting in cracks in the GaAs layer.
FIGS. 38(a) to 38(e) are sectional views illustrating a method for growing a GaAs layer on an Si substrate in which the generation of cracks is suppressed, as disclosed in U.S. Pat. No. 5,145,793.
Initially, as illustrated in FIG. 38(a), a first GaAs layer 503 is grown on a first surface of an Si substrate 501 by a two-stage growth method and, thereafter, a BN (boron nitride) film 502 is formed on a second surface of the Si substrate 501 at room temperature. In the two-stage growth method, a low temperature buffer layer 100xcx9c400xc3x85 thick is grown at a temperature below 500xc2x0 C. and, thereafter, the wafer is heated to about 700xc2x0 C., which is suitable for the growth of GaAs, and the GaAs layer 503 is grown to a desired thickness. This two-stage growth method suppresses the three-dimensional growth of GaAs, providing a high-quality epitaxial layer.
Then, as illustrated in FIG. 38(b), grooves 504 are formed by selectively removing portions of the first GaAs layer 503. These grooves 504 are easily formed by conventional photolithography and wet etching.
After heating the wafer with the grooves 504 to 700xcx9c800xc2x0 C. (FIG. 38(c)), a second GaAs layer 505 and a third GaAs layer 506 as active layers of the device are successively grown on the wafer by MOCVD (FIG. 38(d)). During the growth, since a spontaneous oxide film is formed on the surface of the Si substrate 501 exposed in the grooves 504, the GaAs crystal is not grown in the grooves but selectively grown on the first GaAs layer 503.
Thereafter, portions of the GaAs layers 503, 505, and 506 in the vicinity of each groove 504 are selectively removed, forming a groove 507 larger than the groove 504. The reason why the groove 507 is formed will be described hereinafter. During growing the second and third GaAs layers 505 and 506 in the step of FIG. 38(d), the source gases reaching the groove 504 do not deposit GaAs on the Si substrate 501. The gases are used for the GaAs growth in the vicinity of the groove 504. Therefore, the thickness of the GaAs layer is increased in the vicinity of the groove, and especially the opposite edges of the groove are sharply swollen. Since mechanical stress is concentrated in this swollen part, cracks are generated from this part. The groove 507 is formed by selectively removing the swollen part.
In addition, the BN film 502 on the second surface of the Si substrate suppresses the warpage of the wafer.
As shown in FIG. 40, the generation of cracks in the GaAs layer grown on the Si substrate is closely related with the thickness of the GaAs layer. More specifically, the cracks start to occur when the thickness of the GaAs layer exceeds 3 xcexcm and increase with an increase in the thickness of the GaAs layer. Most of the cracks are generated from the abnormally grown part of the GaAs layer at the edge of the wafer.
Therefore, in the prior art method illustrated in FIGS. 38(a)-38(e), the first GaAs layer 503 thinner than 2 xcexcm, that is hardly cracked, is grown first and then the grooves 504 are formed surrounding a region where a device is to be formed (hereinafter referred to as a device region). Thereafter, the second GaAs layer 505 and the third GaAs layer 506 as active regions of the device and the third GaAs layer 506 are successively grown on the first GaAs layer 503. Therefore, the grooves 504 prevent the cracks produced at the edge of the wafer from reaching the device region.
However, this prior art method has the following problems.
FIGS. 39(a) and 39(b) are diagrams for explaining the problems in the prior art method for growing GaAs on Si. In FIG. 39(a), reference numeral 510 designates the GaAs layer and numeral 511 designates cracks. In our experiment, most of the cracks in the GaAs layer are produced from the edge of the wafer and stopped by the grooves 504 before reaching the device region. However, we found more than ten cracks in the 5 cmxc3x975 cm region inside the grooves. On investigation, it was found that the source of these cracks is a rhombic pit shown in FIG. 39(b) which is produced from the interface between the first GaAs layer 503 and the second GaAs layer 505.
The case of the rhombic pit will be described. After the growth of the first GaAs layer 503, the grooves 504 are formed by conventional photolithography and wet etching. In this process, a photoresist deposited on the wafer is not completely removed but partially remains on the wafer as impurities that cause the rhombic pit. Generally, cleaning the surface of the GaAs layer is rather difficult compared to cleaning the surface of the Si substrate, so that it is very difficult to clean the surface of the GaAs layer which is once contaminated by the deposition of the photoresist and the like. However, it is necessary to separate the device region from the wafer edge by the grooves 504 to prevent the cracks produced at the edge of the wafer from reaching the device region.
As a solution to the above-described problem, a GaAs growth on an Si substrate which is previously patterned using an insulating film is proposed. In this method, however, polycrystalline GaAs is unfavorably deposited on the insulating film during growing the low temperature buffer layer. Generally, it is difficult to favorably perform a selective growth at a temperature below 500xc2x0 C., and the polycrystalline material is deposited on the insulating film. If a GaAs layer is grown on the polycrystalline material at a temperature of about 700xc2x0 C., another polycrystalline material is produced. As the result, crystals grown on the surface of the wafer are connected to each other, so that the isolation of the region patterned by the insulating film is impossible. Therefore, the cracks produced from the wafer edge unfavorably reach the device region through the polycrystalline on the insulating film.
An object of the present invention is to provide a method for producing a semiconductor device in which gas etching is combined with a crystal growth using MOCVD, which provides a clean regrowth interface of AlGaAs and prevents the segregation of impurities on the regrowth interface.
Another object of the present invention is to provide an AlGaAs etching technique using a chlorine containing gas which provides an etching surface as smooth as a cleavage plane.
A further object of the present invention is to provide a method and apparatus for etching a compound semiconductor, in which the etching is controlled to a one atomic layer level and a smooth etching surface is attained.
Another object of the present invention is to provide a method for fabricating quantum wire structures with high uniformity and high controllability.
Still another object of the present invention is to provide a method for fabricating a semiconductor laser in which resonator facets are formed by etching, which facets are perpendicular to the resonator length direction, optically very flat, as smooth as a mirror, and are not physically damaged.
Yet another object of the present invention is to provide a method for fabricating a semiconductor laser in which a flat surface is attained after the crystal growth, which flat surface facilitates processing after the crystal growth and secures high reliability even if the junction-down bonding is employed.
A still further object of the present invention is to provide a method for growing a crystal layer on a different kind substrate in which a favorable selective growth is performed on a substrate with an insulating film pattern, at a temperature lower than 500xc2x0 C., without producing cracks in a region where a device is to be formed.
Other objects and advantages of the present invention will become apparent from the detailed description given hereinafter; it should be understood however, that the detailed description and specific embodiment are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.
According to a first aspect of the present invention, in a method for producing a semiconductor device, a compound semiconductor cap layer including no aluminum is grown on a compound semiconductor layer including aluminum, a mask pattern comprising an insulating film is formed on a part of the compound semiconductor cap layer, the compound semiconductor wafer is immersed in an ammonium sulfide solution, the compound semiconductor wafer is selectively etched away using a chlorine containing gas in a reaction chamber, and a groove formed in the etching process is filled with a compound semiconductor layer in the reaction chamber by MOCVD. Therefore, a regrowth interface on which no impurity is segregated is attained, improving the quality of the regrown layer.
According to a second aspect of the present invention, in a method for producing a semiconductor device, a compound semiconductor cap layer including no aluminum is grown on a compound semiconductor layer including aluminum, a mask pattern comprising an insulating film is formed on a part of the compound semiconductor cap layer, an oxide film on the compound semiconductor cap layer is removed in a reaction chamber, the compound semiconductor wafer is selectively etched away using a chlorine containing gas in the reaction chamber, and a groove formed in the etching process is filled with a compound semiconductor layer in the reaction chamber by MOCVD. Therefore, a regrowth interface on which no impurity is segregated is attained, improving the quality of the regrown layer.
According to a third aspect of the present invention, in a method for producing a semiconductor device including etching an AlxGa1xe2x88x92xAs (0xe2x89xa6xxe2x89xa61) layer by dry etching, the dry etching is a gas etching using a chlorine containing etching gas, a group V gas, and a hydrogen gas which are supplied at the same time. The chlorine containing etching gas is HCl gas or Cl2 gas, the group V gas is arsine (AsH3) gas, tertiary butyl arsine (C4H9AsH2) gas, or trimethylarsine ((CH3)3As) gas. The gas etching is carried out under conditions that a partial pressure of the group V gas is in a range from 8xc3x9710xe2x88x923 Torr to 0.08 Torr and the flow rate of the group V gas to the etching gas is lower than 2.5. Therefore, a very smooth etching surface is attained and the etching surface is not damaged.
According to a fourth aspect of the present invention, in a method for fabricating a semiconductor laser, a plurality of AlxGa1xe2x88x92xAs (0xe2x89xa6xxe2x89xa60) layers are grown on a semiconductor substrate to form a prescribed laser diode structure, an etching mask comprising an insulating film is formed on a part of the laser diode structure, and an oscillation facet of the laser diode is formed by gas etching using an etching gas selected from HCl gas and Cl2 gas, a group V gas selected from arsine (AsH3) gas, tertiary butyl arsine (C4H9AsH2) gas, and trimethylarsine ((CH3)3As) gas, and a hydrogen gas, which are supplied at the same time. The gas etching is performed under conditions that the partial pressure of the group V gas is in a range from 8xc3x9710xe2x88x923 Torr to 0.08 Torr and the flow rate of the group V gas to the etching gas is lower than 2.5. Therefore, a laser oscillation facet as smooth as a cleavage facet is easily formed by the gas etching.
According to a fifth aspect of the present invention, in a method for fabricating a refractive index guide type semiconductor laser with a window structure, a plurality of AlxGa1xe2x88x92xAs (0xe2x89xa6xxe2x89xa60) layers are grown on a semiconductor substrate to form a semiconductor multilayer structure including an active region, a protective film is formed on a part of the semiconductor multilayer structure, the semiconductor multilayer structure is selectively etched away by a gas etching using an etching gas selected from HCl gas and Cl2 gas, a group V gas selected from arsine (AsH3) gas, tertiary butyl arsine (C4H9AsH2) gas, and trimethylarsine ((CH3)3As) gas, and hydrogen, which gases are supplied at the same time, using the protective film as a mask. The gas etching is performed under conditions that the partial pressure of the group V gas is in a range from 8xc3x9710xe2x88x923 Torr to 0.08 Torr and the flow ratio of the group V gas to the etching gas is lower than 2.5. Thereafter, a semi-insulating or high-resistivity semiconductor material having an energy band gap larger than that of the laser oscillation region is grown on opposite sides of a ridge structure formed by the etching process, providing a current blocking structure and a window structure at the same time. After removing the protective film, an ohmic contact layer is grown on the surface of the wafer. Therefore, the semiconductor laser diode having the window layer on the facet is easily fabricated.
According to a sixth aspect of the present invention, a method for producing a semiconductor device including etching a III-V compound semiconductor layer comprises a first etching step including introducing a group V gas and a chlorine containing gas into a reactor so that the chlorine containing gas is supplied in a pulse for a time interval shorter than the supply time of the group V gas, and a second etching step including halting the supply of the group V gas and the chlorine containing gas and purging the inside of the reactor with hydrogen. The first etching step and the second etching step are alternatingly repeated. Therefore, it is possible to control the etching at one-atomic layer level, providing a smooth etching surface.
According to a seventh aspect of the present invention, an apparatus for producing a semiconductor device includes a rotatable disc susceptor on which a semiconductor wafer is disposed, and means for partitioning the surface of the susceptor into a plurality of regions using hydrogen is prepared. At least one of the regions is filled with a gas mixture comprising a group V material hydride gas, a chlorine containing gas, and hydrogen. At least one of the regions is filled with hydrogen. A semiconductor wafer on the susceptor is successively moved through the regions by rotation of the susceptor. Therefore, it is possible to control the etching at one-atomic layer level, providing a smooth etching surface.
According to an eighth aspect of the present invention, in a method for producing a semiconductor device, an apparatus including a rotatable disc susceptor on which a semiconductor wafer is disposed and means for partitioning the surface of the susceptor into a plurality of regions using hydrogen is prepared. At least one of the regions is filled with a gas mixture comprising a group V material hydride gas, a chlorine containing gas, and hydrogen. At least one of the regions is filled with hydrogen. A semiconductor wafer on the susceptor is successively moved through the regions with the rotation of the susceptor. A first etching step is carried out in the region filled with the gas mixture and a second etching step is carried out in the region filled with hydrogen. The first etching step and the second etching step are alternatingly repeated. Therefore, it is possible to control the etching at one-atomic layer level, providing a smooth etching surface.
According to a ninth aspect of the present invention, in a method for producing a quantum wire structure, a first semiconductor layer is formed on a semiconductor substrate with a {100} surface orientation, an etching mask having a stripe-shaped opening extending along a  less than 011 greater than  direction is formed on the first semiconductor layer, the first semiconductor layer is selectively etched etching using an etching gas selected from HCl gas and Cl2 gas, a group V gas selected from arsine (AsH3) gas, tertiary butyl arsine (C4H9AsH2) gas, and trimethylarsine ((CH3)3As) gas, and hydrogen, which gases are introduced into a reactor at the same time. The gas etching is carried out under conditions that the partial pressure of the group V gas is in a range from 8xc3x9710xe2x88x923 Torr to 0.08 Torr and the flow ratio of the group V gas to the etching gas is lower than 2.5, thereby forming a stripe-shaped V groove with side surfaces of {111}B planes. Thereafter, a second semiconductor layer having an energy band gap smaller than that of the first semiconductor layer is formed in the vicinity of the bottom of the V groove, and a third semiconductor layer having an energy band gap larger than that of the second semiconductor layer is formed on the second semiconductor layer.
According to a tenth aspect of the present invention, in a method for producing quantum wire structures, a first high-resistivity layer comprising a first semiconductor is grown on a semiconductor substrate, a second high-resistivity layer comprising a second semiconductor and having an electron affinity smaller than that of the first semiconductor and a third high-resistivity layer comprising same material as the first semiconductor are successively grown on the first high-resistivity layer, and alternating projections and recesses are formed in the second high resistivity layer so that the cross section of each recess is an inverted triangle. The alternating projections and recesses are formed by a gas etching using an etching gas selected from HCl gas and Cl2 gas, a group V gas selected from arsine (AsH3) gas, tertiary butyl arsine (C4H9AsH2) gas, and trimethylarsine ((CH3)3As) gas, and hydrogen, which are introduced into a reactor at the same time, under conditions that the partial pressure of the group V gas is in a range from 8xc3x9710xe2x88x923 Torr to 0.08 Torr and the flow ratio of the group V gas to the etching gas is lower than 2.5. Therefore, high-quality quantum wires are. formed with high controllability.
According to an eleventh aspect of the present invention, in a method for fabricating a semiconductor laser, at least a first conductivity type AlyGa1xe2x88x92yAs cladding layer, an AlzGa1xe2x88x92zAs (0xe2x89xa6z less than y) active layer, a second conductivity type AlwGa1xe2x88x92wAs (z less than w) cladding layer, and a first conductivity type GaAs current blocking layer are successively grown on a first conductivity type GaAs substrate with a {100} surface orientation, an insulating film having a stripe-shaped opening extending along a  less than 011 greater than  direction is formed on the semiconductor wafer after the crystal growth process, the semiconductor wafer is selectively etched away by vapor phase etching with a chlorine containing gas using the insulating film as a mask, forming a stripe-shaped groove with side surfaces of {111}B planes and a bottom surface of the second conductivity type cladding layer, and a second conductivity type AlwGa1xe2x88x92wAs layer is grown in the stripe-shaped groove. Since no crystal is grown on the {111}B planes, the groove is filled with the crystal layer grown from the bottom surface of the groove, resulting in a flat surface of the wafer.
According to a twelfth aspect of the present invention, in a method for fabricating a semiconductor laser, at least a first conductivity type AlyGa1xe2x88x92yAs cladding layer, an AlzGa1xe2x88x92zAs (0xe2x89xa6z  less than y) active layer, and a second conductivity type AlwGa1xe2x88x92wAs (z less than w) cladding layer are successively grown on a first conductivity type GaAs substrate with a {100} surface orientation, a stripe-shaped insulating film pattern extending along a  less than 011 greater than  direction is formed on a part of the semiconductor wafer after the crystal growth process, an oxide film on the surface of the semiconductor wafer is removed by an ammonium sulfide treatment or a surface cleaning conducted in a reaction chamber, the semiconductor wafer is selectively etched away by vapor phase etching with a chlorine containing gas using the insulating film pattern as a mask, forming a stripe-shaped ridge structure with side walls of {111}B planes, and a current blocking layer is formed on opposite sides of the ridge structure contacting the side walls. Therefore, a highly-reliable AlGaAs buried heterojunction laser is achieved.
According to a thirteenth aspect of the present invention, in a method for epitaxially growing a III-V compound semiconductor layer on a substrate with an insulating film pattern by MOCVD, the epitaxial growth is carried out while supplying source gases and HCl gas or Cl2 gas at the same time under the condition that the molar flow ratio of the HCl gas or Cl2 gas to the group III gas is lower than 0.3.
According to a fourteenth aspect of the present invention, in a method for epitaxially growing a semiconductor layer comprising a second semiconductor material on a semiconductor substrate comprising a first semiconductor material by MOCVD, an insulating film is deposited on the semiconductor substrate and patterned so as to surround a region of the semiconductor substrate on which a device is to be produced, a low temperature buffer layer comprising the second semiconductor material is grown on the semiconductor substrate while supplying source gases and HCl gas or Cl2 gas at a temperature lower than 500xc2x0 C., the semiconductor layer comprising the second semiconductor material being grown at a temperature higher than 600xc2x0 C. Therefore, cracks produced in the semiconductor layer grown on the different kind of semiconductor substrate are suppressed.
According to a fifteenth aspect of the present invention, in the method for epitaxially growing the low temperature buffer layer comprising the second semiconductor material, the molar flow ratio of the HCl gas or Cl2 gas to the group III gas is lower than 0.3. Therefore, cracks produced in the semiconductor layer grown on the different kind of semiconductor substrate are suppressed, and a high-quality crystal layer is grown on the substrate.